Integrated circuits, including dies, for example, imager dies such as charge-coupled-devices (CCD) and complementary metal oxide semiconductor (CMOS) dies, have commonly been used in photo-imaging applications.
Imager dies, such as the CMOS imager die, typically contain thousands of pixels in a pixel array on a single chip. Pixels convert light into an electrical signal that can then be stored and recalled by an electrical device such as, for example, a processor. The electrical signals that are stored may be recalled to produce an image on, for example, a computer screen or a printable media.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, each of which being assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a block diagram of an imager die 10, having a CMOS imager device 8 formed therein. The CMOS imager device 8 has a pixel array 15 that comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixel cells of each row in the pixel array 15 are all turned on at the same time by a row select line, and the pixel cells of each column are selectively output by respective column select lines. A plurality of row and column lines is provided for the entire pixel array 15. The row lines are selectively activated in sequence by a row driver 1 in response to a row address decoder 2 and the column select lines are selectively activated in sequence for each row activation by a column driver 3 in response to a column address decoder 4. The CMOS imager device 8 is operated by the control circuit 5, which controls the address decoders 2, 4 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 1, 3 for applying driving voltages to the drive transistors of the selected row and column lines.
The pixel output signals typically include a pixel reset signal Vrst taken from a charge storage node when it is reset and a pixel image signal Vsig, which is taken from the storage node after charges generated by an image are transferred to the node. The Vrst and Vsig signals are read by a sample and hold circuit 6 and are subtracted by a differential amplifier 7 that produces a difference signal (Vrst-Vsig) for each pixel cell, which represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter (ADC) 9. The digitized pixel difference signals are then fed to an image processor 11 to form and output a digital image. In addition, as depicted in FIG. 1, the CMOS imager device 8 may be included on a single semiconductor chip to form the imager die 10.
A partial cross-sectional view of a conventional pixel cell 13 that could be incorporated into the pixel array 15 of FIG. 1 is illustrated in FIG. 2. The illustrated pixel cell 13 typically includes a photosensor 12 having a p-region 12a and n-region 12b in a p-type substrate 14. The substrate 14 is typically a p-type silicon substrate. The p-region 12a of the photosensor 12 is typically coupled to the potential of the p-substrate 14 for efficient operation of the photosensor 12. The pixel cell 13 also includes a transfer transistor with associated gate 16, a floating diffusion region 18 formed in a more heavily doped p-type well 20, and a reset transistor with associated gate 22. The reset transistor 22 has an associated source/drain region 30 connected to a supply voltage Vaa-pix that is used to reset the floating diffusion region 18 to a predetermined charge level (i.e., supply voltage Vaa-pix level) prior to charge transference.
In operation, incident light 36 from a light source 38 striking the surface of the p-region 12a of the photosensor 12 generates electrons that are collected in the n-region 12b. When the transfer gate 16 is on, the generated electrons in the n-region 12b are transferred to the floating diffusion region 18 as a result of the potential difference existing between the photosensor 12 and the floating diffusion region 18. The floating diffusion region 18 is coupled to the gate of a source follower transistor 24, which receives the charge stored by the floating diffusion region 18 and transfers a voltage corresponding to the charge to a first source/drain terminal of a row select transistor 26. When a row select control signal RS goes high, the voltage corresponding to the generated charge is transferred to the column line 28 where it is further processed by sample/hold and processing circuits such as the sample and hold circuit 6 (FIG. 1).
The illustrated pixel cell 13 is formed between two isolation regions, or shallow trench isolation (STI) regions 32. The STI regions 32 prevent crosstalk between adjacent pixels, as pixel cell 13 is only one of hundreds or thousands of pixels that can be incorporate into the pixel array of an imager die (e.g., pixel array 15 of imager die 10 (FIG. 1)).
The pixel cell 13 is typically formed with an oxide layer 34 over the surface of the substrate 14. Various other layers (not shown) are typically deposited over the pixel cell 13. For example, a tetraethyl orthosilicate (Si(OC2H5)4) (TEOS) layer may be deposited over the oxide layer 34. Similarly, a boro-phospho-silicate glass (BPSG) layer could be deposited over the TEOS layer. A metallization layer and insulating layer can also be deposited over the pixel cell 13.
One adverse effect of depositing the oxide layer 34 over the substrate 14 is the reflection of incident light 36. In operation, incident light 36 from the light source 38 encounters the oxide layer 34 before striking the p-region 12a of the photosensor 12. The index of refraction for the oxide layer can be as low as 1.6; whereas the index of refraction of the substrate 14 (formed of silicon) can be as high as 4.0. The abrupt transition from an index of refraction of 1.6 to 4.0 results in a high percentage of incident light reflection 40. The percentage of incident light 36 that is reflected can be determined using the following formula:Reflection=|X−Y|2/(X+Y)2;  (1)wherein X represents the index of refraction of the oxide layer 34, and Y represents the index of refraction of the substrate 14. In the above-described example, the reflection percentage is |4.0-1.6|2/(4.0+1.6)2˜18%. Therefore, the photosensor 12 fails to capture approximately 18% of the incident light 36 to which it is exposed. This is undesirable.
Accordingly, there is a desire and need for a pixel cell that can capture a greater percentage of incident light by reducing the percentage of incident light that is reflected.